The highest goal, stated honestly
Families ask what the top of this path looks like. The honest answer: there is no youth chip-design competition whose gold medal is treated like a gold at the International Mathematical, Physics or Informatics Olympiads, and we will not describe one. The realistic highest goals for a YSRP project are a top award at an established international research competition—Regeneron ISEF above all—or a professional paper with a genuine original contribution. Those are the targets the research track is built around.
“Allowed to use a custom chip”, “credible competition” and “recognisable to universities” are three different things, and the tables on this page keep them apart. Universities read achievements in the context of a student’s opportunities; MIT says so explicitly and publishes no points table for awards. What a reader looks for is a student who can explain, verify and keep improving their own work. The chip is evidence of that ability. An award is an external judge’s confirmation of one specific piece of work.
YSRP uses custom chips and intelligent systems as the vehicle for building young people’s capacity for original research—supporting them towards ISEF and the other major science competitions, open-hardware robotics competitions, and professional publication where the research has matured to that level.
| Certainty | Outcome | How we describe it |
|---|---|---|
| Every student | A chip of their own design; a working FPGA prototype; engineering notebook and design document; disclosure statement; public project page; certificate and cohort showcase. | Written into the enrolment agreement. |
| Supported by the outcomes pack | Entry through the regional ISEF-affiliated fair; an open-hardware robotics competition (WRO Future Innovators, WRO Future Engineers, RoboCupJunior Rescue Maze); submission to a peer-reviewed student journal or an open-hardware conference. | Each cohort’s participation and acceptance figures are published once they exist. |
| The highest goals (research track) | Top awards at Regeneron ISEF; Regeneron STS, EUCYS, the Yau Science Award or Davidson Fellows where eligible; for the rare mature project, a professional paper at FPGA, DAC, ICCAD or ICRA. | Named here as targets. Reached only by the student’s own work; described afterwards only through real examples with the family’s consent. |
Tier one: the international research competitions
These are the honours we treat as the highest goals. The achievement level matters as much as the name: an ISEF finalist, a first award in category and a top-of-fair award are different results, and a Special Award is separate from the Grand Awards. Application documents must state the award, its scope and the student’s own contribution precisely.
| Competition / honour | Level to aim for | Fit for a custom-chip project | Main eligibility |
|---|---|---|---|
| Regeneron ISEF International Science and Engineering Fair | Top-of-fair awards and first awards in category; other Grand Awards stated precisely | Very strong. Chips, embedded systems, sensing, control and robotics research | Grades 9–12 or equivalent; under 20 on the stated date; selected through an affiliated fair |
| Regeneron STS Science Talent Search | Top 40 finalist, Top 10 | Very strong for deep individual research | Final year of high school; US schooling and residence, or US citizens abroad under its rules; no team projects |
| EUCYS EU Contest for Young Scientists | The main prizes, first prize above all | Very strong for engineering research | Ages 14–20; nominated by a national competition, not open entry |
| Yau Science Award | Main prizes at the global final, distinguished from regional rounds | Strong where the chip work has an original computational method, architecture or theoretical contribution | High-school students worldwide; by division rules |
| Davidson Fellows | Selection as a Fellow (a research scholarship, not a fair medal) | Strong for complete, deep engineering work | Under 18; mainly US citizens or permanent residents living in the US, with a military-family exception |
| Thermo Fisher Junior Innovators Challenge | Top 30 and main awards; Top 300 and nomination are separate | Strong for middle-school engineering research | US grades 6–8; nominated from the top 10% of an affiliated fair |
| 3M Young Scientist Challenge | National final and main prizes | Good for an invention that solves an everyday problem with a chip inside, though the chip need not be the centre | US legal residents in grades 5–8; individual entries |
For students from different countries, ISEF is the main research line; for final-year students who meet the US requirements, STS is worth aiming at alongside it. Middle-school students build research ability first, then choose JIC, a regional fair or an open-hardware robotics competition as their eligibility allows.
Why ISEF fits a chip project
ISEF can judge the chip research itself. Its Embedded Systems category covers circuits, microcontrollers, sensors and signal processing; a student may present a digital circuit or ASIC of their own design and offer an FPGA implementation, physical silicon or a complete system as evidence, with no required brand of controller. A good project asks a question such as “can this design reduce the latency and energy of a robot’s sensor processing under stated conditions?” and then compares a bought microcontroller, the FPGA implementation and the ASIC, rather than only showing that a chip was made. The judging criteria reward the question, the alternatives considered, the testing, the creativity, and the student’s understanding and independence.
There is precedent. The official ISEF 2026 Special Awards list includes “Design and Evaluation of an FPGA-Based Interconnect for Energy-Efficient Data Center Operation”. That shows FPGA and hardware-architecture research has room to compete and win; it is an FPGA project and a special award, and we do not describe it as a custom ASIC taking the top prize.
Robotics competitions: replace the controller, or add your own module?
The common belief that robotics competitions forbid custom hardware is true of some and not of others. The distinction that matters is between replacing the main controller and adding a sensing or computing module of the student’s own.
| Competition / division | Room for a custom chip or controller | Our advice |
|---|---|---|
| WRO Future Innovators | Free choice of controller, motors, sensors and materials; the project must fit the season’s theme | First choice among robotics competitions. Solve a real problem with the student’s chip and show the research, application and design. Age groups 8–12, 11–15 and 14–19 |
| WRO Future Engineers | Any robot, controller and materials within the rules; currently an autonomous-driving challenge | Suited to ages 14–22 researching real-time control, sensing and low-latency computation |
| RoboCupJunior Rescue Maze | 2026 rules allow robots built from raw hardware and require the design and build to be mainly the student’s own | Excellent for deep engineering. International division ages 14–19. Note: kits or sensing parts designed or marketed for the task are prohibited, so YSRP teaches students to design and verify their own modules and does not sell a “rescue chip” |
| RoboCupJunior Soccer, Rescue Line, OnStage | Each division has its own rules; the Maze rules do not transfer | Candidates; confirm age, hardware and scoring division by division |
| WRO RoboMission | The current category page lists free hardware choice; regional and seasonal rules vary | No longer safe to say “LEGO only”; check the specific local event |
| FIRST Robotics Competition (FRC) | 2026 rules specify the main controller and allow regulated custom circuits | Research a sensing or co-processing module; the official control system cannot be replaced |
| FIRST Tech Challenge (FTC) | The 2025–26 rules specify the control system and limit how custom circuits connect and are powered | Some design room; check the full rules for the season before entering |
| VEX V5 Robotics Competition | 2026–27 rules require the V5 Robot Brain and exclude other microcontrollers | Not a destination for a custom chip as the robot’s controller |
WRO Future Innovators starts at age 8–12, so a younger sibling can begin there. Its world-final prizes can showcase excellent engineering, but “Olympiad” in the name does not make its selection or its university recognition equivalent to the IMO or IOI, and we say so.
Where to enter, by where the student studies
Attending sessions in Singapore or fabricating a chip in Taiwan does not by itself make a student eligible for either country’s national selection. Entry depends on where the student is enrolled, and the route must be confirmed before hardware and fabrication dates are fixed.
| Where the student studies | First place to look | How a chip project fits |
|---|---|---|
| Taiwan | Taiwan International Science Fair (TISF); the national primary and secondary school fair for middle-school students | TISF selects Taiwan’s international representatives; confirm nationality, grade and submission rules for the year |
| Singapore | Singapore Science and Engineering Fair (SSEF) | The research route; officially for MOE-school students, so an international-school student should not be assumed eligible |
| Hong Kong | Hong Kong Youth Science and Technology Innovation Competition and its ISEF selection | Original engineering projects; international places are selected by the organiser under its rules |
| Japan | JSEC; the Japan Student Science Award | Both lead to ISEF; check schooling and double-entry restrictions |
| United States | The local ISEF-affiliated fair; JIC in middle school, STS in the final year | Routes split by grade, location and form of research |
| Canada | Canada-Wide Science Fair (CWSF) | Selected through regional STEM fairs for grades 7–12 and Cégep; check the year’s international-selection procedure |
| Germany | Jugend forscht; Jugend forscht junior | Engineering research; divisions from age 15 and under 14, with residence, schooling and registration conditions |
| Elsewhere | The ISEF affiliated-fair network and the national EUCYS nominating body | Start from the official selection network; a general “international invention show” is not a substitute |
Professional publication, chosen by contribution
A professional paper and a fair award are parallel routes; a student does not need a medal before submitting. A secondary-school author is held to the same standard as anyone else, and acceptance depends on the paper alone. Registration and attendance for authors under 18 must be confirmed with each conference. Peer-reviewed papers, workshop papers, abstracts, demonstrations, competition technical reports and arXiv preprints represent different levels of review, and “presented at” must never be written as “published at”.
| Venue | Research it looks for | Realistic position for a secondary-school author |
|---|---|---|
| ISSCC | New circuits, chip architectures, energy efficiency or other major performance advances, with concrete measurements | The hardest target in the field; an educational tape-out alone is far from a contribution |
| DAC (Research Track) | EDA, verification, chip design, architecture, hardware security, AI and hardware | Suitable for a new method with solid comparisons; an Engineering Track demonstration is not a research paper |
| ICCAD | Design automation, synthesis, verification, physical design, system-level methods | Better suited to a student who proposes a new design or verification method than to a finished ASIC alone |
| ACM/SIGDA FPGA | FPGA architecture, tools, accelerators and spatial computing | Can be attempted before the ASIC returns; must still go beyond an ordinary application |
| IEEE ICRA | Robot perception, control, systems and experimental research | The chip must deliver an explainable robotics contribution; swapping a controller is not enough |
Most students will first publish in a student venue or present at an open-hardware conference; that is a real result and a good first paper.
| Venue | Type | Fit |
|---|---|---|
| Journal of Emerging Investigators | Peer-reviewed journal for middle- and high-school research | Asks for a question, a method and data; the comparison of measured silicon with simulation is exactly its format |
| Journal of Student Research; STEM Fellowship Journal | Student journals | A first publication; we help families judge quality and fees |
| Free Silicon Conference, ORConf, Latch-Up | Open-hardware conferences | Talks and posters; young presenters are welcomed and remembered |
| IEEE student branches and regional student-paper contests | Student papers | For senior students; MTRI researchers can advise |
| arXiv (cs.AR) | Preprint | For exceptional projects, with an MTRI endorsement, as a public record of a competition entry |
| Engineering-education venues (IEEE FIE, MSE, EDUCON) | MTRI’s research on the programme | Students may be co-authors where their contribution warrants it; this does not replace the student’s own chip research |
Research directions that serve fairs, robotics and papers at once
The directions below are suggestions, not records of advantage or awards. Comparisons must state clock, process, supply, precision, workload and measurement boundaries; a purpose-built circuit doing a tiny task cannot be reported as “outperforming a general-purpose MCU”.
| Direction | What the student designs | What must be proved | First targets |
|---|---|---|---|
| Low-power event sensing | Event filtering, wake-up and data-compression logic | Lower energy or transmitted data at a comparable miss rate | ISEF; DAC or FPGA once mature |
| Real-time sensor co-processing for robots | Encoder synchronisation, time-stamping, digital filtering | Better latency, jitter and control error | ISEF; WRO Future Engineers; a suitable RoboCupJunior division |
| A small edge-AI accelerator | A limited quantised or sparse compute unit | Time, energy or resource saved against a baseline at the same task and accuracy | ISEF; FPGA; later DAC or ICCAD |
| Hardware security and reliability | Error detection, fault tolerance or protection modules | Detection rate and protection against area and latency cost | ISEF; DAC; ICCAD |
| Low-latency financial stream processing | Fixed-point moving averages, a crossover detector and a pre-trade risk check updated once per tick | Latency, jitter and energy per tick against a microcontroller and an FPGA; the accuracy cost of fixed-point arithmetic | ISEF; the Yau Science Award for a mathematical version; FPGA. Worked example ↗ |
| Assistive smart devices | Sensing and control logic integrated into a complete device | A real use case, reliable measurements and a demonstrated improvement | ISEF; WRO Future Innovators |
Three routes by age, and the product that fits each
The twelve-week programme and the outcomes pack cover the first two routes. The research track exists for the few students whose work is ready for ISEF-level awards or a professional venue; it is scoped and priced per project after a review of the work, because that is the only honest way to sell it.
| Route | Ages | What the work looks like | Targets | YSRP product |
|---|---|---|---|---|
| Creation and understanding | 12–13 | Logic, FPGA, a small robot and a proper test record | WRO Future Innovators junior groups; the local science fair; JIC or 3M for US-eligible students | Twelve-week programme |
| Original engineering research | 14–17 | A question, alternatives, measurements and a written study | The ISEF-affiliated fair as the main line; WRO, RoboCupJunior or the Yau Science Award by project; confirm eligibility and rules before fixing hardware and fabrication dates | Programme + outcomes pack |
| Professional publication | The mature few | A gap in the literature, baseline comparisons and reproducible experiments | FPGA, DAC, ICCAD, ICRA; ISSCC only for work that meets its circuit-innovation and measurement bar | Research track, scoped and priced per project after review |
AI, disclosure and the 2027 ISEF rules
The 2027 ISEF rules allow AI as a research resource when it is disclosed, and do not allow generative AI to write the research plan, the abstract, the poster or the citations. YSRP’s studio is built to that rule: it keeps the records, provides the structure, points out what is missing and helps the student understand, and it does not produce fair documents at the press of a button. Judges reward a clear question, sound method, real data and a student who can explain every decision; they penalise work that is not the student’s own or cannot be explained. Families should expect each competition’s forms to be completed accurately, including where the work was done and who advised.
Magellan Global and MTRI intend to sponsor independent special awards for custom-silicon projects at established fairs. Judging for any such award is carried out by people with no connection to YSRP.
Beyond the award
Most of what a student keeps is not a medal. It is the ability to say how something is made, a project page that can be found and read, a notebook that records how their thinking changed, a week among engineers in Taipei, and the confidence to begin the next question. Those are the knowledge, judgement and opportunity the group describes as Mobility Capital, and they are the outcomes we design for.
Rules checked in November 2026 against the official pages: ISEF rules · ISEF Embedded Systems · ISEF judging criteria · ISEF awards · ISEF 2026 special awards · affiliated-fair network · STS · EUCYS · Yau Science Award · Davidson Fellows · JIC · 3M · WRO categories · WRO 2026 season · RoboCupJunior Rescue Maze 2026 · RoboCupJunior general rules · FRC 2026 manual · FTC manual · VEX V5 rules · TISF · SSEF · Hong Kong ISEF selection · JSEC · CWSF · Jugend forscht · ISSCC · DAC · ICCAD · FPGA · ICRA · MIT admissions on extracurriculars. Some 2027 rules are not yet final; eligibility, age bands and hardware rules must be confirmed each year for the specific event and region.