The question
Trading firms use purpose-built hardware because a computer running software cannot promise to answer every incoming price within a fixed few hundred nanoseconds. The example asks a question a fourteen-year-old can state and test: for a stream of price ticks and a fixed set of rules, how much lower are the latency, jitter and energy per tick of a purpose-built circuit than of a microcontroller or an FPGA, and what does fixed-point arithmetic cost in accuracy?
The rules are an input, not the point. The project makes no claim that the rules make money, and no student trades. What is being studied is how a stream of numbers becomes a decision in hardware—the same question that sits under high-frequency trading, under sensor fusion in a robot, and under every event detector that must never miss a beat.
What the chip does
The development board streams historical price and volume ticks into the chip. In a single clock cycle the chip:
- updates a fast and a slow exponential moving average in fixed-point arithmetic;
- detects when the two averages cross, and raises a signal pin;
- runs a pre-trade risk check—position limit, order-size limit and a price band—and raises a separate “blocked” pin when a rule would be broken;
- starts a hardware latency counter that stops when the signal appears, so the delay can be read directly.
Stretch options for students who want more: a volume-weighted average price, or a four-level order book updated in one cycle. The core design is a few thousand logic cells and fits a single tile of the shared wafer, with room to spare.
How the twelve weeks map onto it
The example follows the standard YSRP calendar. The sequence is the same for every student; the parameters, the data and the question are theirs.
| Weeks | The example project | What the student has at the end |
|---|---|---|
| 1–4 | Logic, timing and fixed-point numbers. The first moving-average filter on the Studio’s block canvas. A Python model of the same filter to compare against. | A filter that runs in simulation and matches the model |
| 5–8 | The student’s own version on the FPGA board, fed real tick data from a laptop. The crossover detector and the risk check are added. First latency measurements with the on-chip counter and an oscilloscope. | A working prototype and the first page of real measurements |
| 9–12 | Verification against corner cases; the microcontroller and FPGA comparisons; energy per tick; the engineering notebook and design document. Cohort showcase. | A finished study and a design cleared for fabrication |
| 13 | Fabrication submission on two booked routes. | A submission record and the expected return window |
| +6–9 months | The chip returns. The student runs the same tick stream through their silicon and compares it with simulation and with the FPGA. | Measured silicon, and the results section of the study |
Make it your own
No two students submit the same project, and competitions require that they do not. The example gives the method; each student changes at least one of the following and must justify the choice in their notebook. The question is the student’s.
| Change one of these | Examples | Why it makes the project the student’s own |
|---|---|---|
| The indicator | EMA crossover; RSI; VWAP; a simple Kalman filter; a volatility band | Different arithmetic, different precision trade-offs, different results |
| The market and the data | Equities, FX, crypto, electricity prices, a sensor stream treated the same way | Different tick rates and value ranges change the design |
| The arithmetic | Bit width, rounding, shift-based versus multiplier-based averaging | The accuracy-against-area trade-off is the heart of the study |
| The risk rules | Position limit, order size, price band, a cool-down timer | A different state machine and a different set of corner cases |
| The comparison | Which microcontroller, which FPGA, which clock | The measurement design is part of the research |
What the Studio does, and what the student does
On the YSRP Studio—Magellan Global’s AI-assisted design-automation platform, built by Magellan Silicon, the group’s semiconductor engineering team in Taipei, on open-source tools—the student draws the design, chooses every parameter and reads every result. The Studio’s assistant explains the fixed-point arithmetic, generates test vectors from the student’s own data, runs synthesis, simulation, layout and the pre-fabrication checks, and translates the reports into plain language. It asks why before it helps, records every exchange, and produces the disclosure statement that science fairs require.
It does not write the research plan, the abstract or the poster. The 2027 ISEF rules do not allow that, and neither do we.
What the student measures
Every comparison states clock, bit width, workload and measurement boundaries. A 130 nm student chip at tens of megahertz is not faster than a trading firm’s FPGA in absolute terms; the result that matters is the architecture—cycles per tick and energy per tick—and the student’s ability to explain it.
| Measurement | How it is taken | Compared with |
|---|---|---|
| Latency from the last bit of a tick to the signal pin | On-chip counter read by the board; confirmed on an oscilloscope | Microcontroller (C) and FPGA versions of the same rules |
| Jitter across ten thousand ticks | Distribution of the counter values | Same |
| Energy per tick | Supply current at a fixed tick rate, divided by ticks | Same |
| Fixed-point error | Difference from a floating-point Python reference over the whole data set | The student’s own bit-width choices |
| Silicon versus simulation | The same stream through the returned chip | The pre-fabrication simulation and the FPGA |
Where this project can go
Regeneron ISEF’s Embedded Systems category, through the student’s regional affiliated fair; the Yau Science Award for a version with a stronger mathematical contribution; a first paper in the Journal of Emerging Investigators; a poster at an open-hardware conference. These are routes, not promises. Eligibility, achievement levels and the full list of venues ↗
For parents
Your child will finish with a chip they designed, a working FPGA prototype, measured data, an engineering notebook and a written study—and the ability to explain, step by step, how a stream of numbers became a signal in hardware. That explanation is what judges, teachers and admissions readers respond to, and it is the part no kit can supply.
If your child’s interest is robots, energy, music or the environment rather than markets, the same method applies: the research directions on the outcomes page list five other starting points, and every cohort begins by choosing the student’s own question.